The invention relates to the design and manufacture of integrated circuits, and more particularly, to systems and methods for performing physical verification during the circuit design process.
The electronic design process for an integrated circuit (IC) involves describing the behavioral, architectural, functional, and structural attributes of an IC or electronic system. Design teams often begin with very abstract behavioral models of the intended product and end with a physical description of the numerous structures, devices, and interconnections on an IC chip. Semiconductor foundries use the physical description to create the masks and test programs needed to manufacture the ICs.
A Physical Verification (PV) tool is a common example of an EDA tool that is used by electronics designers. PV is one of the final steps that is performed before releasing an IC design to manufacturing. Physical verification ensures that the design abides by all of the detailed rules and parameters that the foundry specifies for its manufacturing process. Violating a single foundry rule can result in a silicon product that does not work for its intended purpose. Therefore, it is critical that thorough PV processing is performed before finalizing an IC design. Physical Verification tools may be used frequently and at many stages of the IC design process. PV tools may be used during design and at tape-out to ensure compliance with physical and electrical constraints imposed by the manufacturing process. In addition, PV tools may also be used after tape-out to verify and ensure manufacturability of the design and its constituent elements.
PV tools read and manipulate a design database which stores information about device geometries and connectivity. Because compliance with design rules generally constitutes the gating factor between one stage of the design and the next, PV tools are typically executed multiple times during the evolution of the design and contribute significantly to the project's critical path. Therefore, reducing PV tool execution time makes a major contribution to the reduction of overall design cycle times.
As the quantity of data in modern IC designs become larger and larger over time, the execution time required to process EDA tools upon these IC designs also becomes greater. For example, the goal of reducing PV tool execution time is in sharp tension with many modern IC designs being produced by electronics companies that are constantly increasing in complexity and number of transistors. The more transistors and other structures on an IC design, the greater amounts of time that is normally needed to perform PV processing. This problem is exacerbated for all EDA tools by constantly improving IC manufacturing technologies that can create IC chips at ever-smaller feature sizes, which allows increasingly greater quantities of transistors to be placed within the same chip area, as well resulting in more complex physical and lithographic effects during manufacture.
To achieve faster results, it is therefore desirable to perform EDA processing upon an IC layout using multi-processing approaches, e.g., concurrent or parallel processing. Examples of systems that support parallel processing include multi-CPU/processor computers and distributed processing systems having multiple networked nodes.
There are, however, significant obstacles for EDA vendors that wish to implement a parallel processing solution for IC layouts. Consider an example parallel processing approach in which an EDA tool geometrically divides an IC layout into multiple areas/portions and independently processes each portion using a different CPU. Such an approach is shown in FIG. 1 in which an example IC layout 107 has been divided into multiple geometric layout areas/portions 107a, 107b, 107c, and 107d. For PV processing, each layout portion 107a, 107b, 107c, and 107d may be processed for DRC correctness using a separate processor or CPU. Polygon 101 is located on a first layer and extends across all four layout portions 107a-d. Polygon 103a-d all reside on a second layer. Polygon 103a is located in layout portion 107a. Polygon 103b is located in layout portion 107b. Polygon 103c is located in layout portion 107c. Polygon 103d is located in layout portion 107d. 
Consider further if the PV tool needs to perform geometric operations across multiple layout portions. An example of a geometric operation that is commonly performed by PV tool is the “polyEnclose” operation that selects polygons on a first layer (layerA) that enclose polygons on a second layer (layerB). This operation may be performed with count-based select to identify polygons on the first layer that enclose a specific number of polygons on the second layer.
The problem that arises is that the separate processors handling the different layout portions individually will not have enough information within its own respective layout portion to adequately perform the required processing. With respect to the example of FIG. 1, assume that the polyEnclose operation is performed to identify all objects on a first layer that encompass four objects on the second layer. Here, it can clearly be seen that polygon 101 on the first layer encompasses four polygons 103a-d on the second layer. Therefore, the correct result is that polygon 101 is selected.
However, polygon 101 also extends across multiple layout portions 107a-d. Assuming each layout portion 107a-d has been assigned to a different processor for processing, the data corresponding to any single layout portion may not provide enough information that would allow its corresponding processing entity to know the entire boundary of the polygon 101 or the number of polygons on the second layer that fall within that boundary. As can be seen from this simple example, the output of the select operation depends not only on the input data in the current layout portion, but also on the input data in other layout portions as well. Therefore, none of the processing entities would separately have enough data to make the proper identification of polygon 101 if each layout portion 107a-d is processed independently.
The present invention provides a method, system, and computer program product for facilitating multi-processing of IC designs and layout. In some embodiments, the invention provides an approach for handling geometric select operations in which data for different layout portions may be shared between different processing entities. The approach comprises the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count aggregation for count-based select operations; and select phase two operations for combining results of selecting internal shapes and interface shapes.
Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims. Both the foregoing general description and the following detailed description are exemplary and explanatory, and are not intended to be limiting as to the scope of the invention.